A VHDL Design Methodology for FPGAs

In order to generate efficient FPGA designs, the HDL description style has to be adapted to the requirements of FPGA architecture. Unlike ASIC targets, FPGAs offer a fixed set of resources which can be used to generate an efficient design. This requires that the HDL source code of a design be adapted to exploit the available resources. Since the structure of synthesized logic is inferred from the description style, the source-level coding has to be adapted to yield optimal designs. Generating optimized designs requires a good understanding of the FPGA target. In addition, the code has to consider the description styles supported by a particular synthesis tool, while the specific hardware description language used is only of minor importance.